1. Field of the Invention
The present invention relates to an insulated gate field effect transistor, a semiconductor device formed by a static random-access memory using this transistor, and a method of manufacturing the semiconductor device.
2. Description of the Related Art Higher speed, higher levels of integration, and lower power consumption of integrated circuits have heretofore been pursued mainly by scaling down a planar type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The sectional structure of an existing planar type MOSFET will be described with reference to a schematic constitution sectional view of FIG. 25.
As shown in FIG. 25, the planar type MOSFET 101 has a gate electrode 113 on a semiconductor substrate 111 with a gate insulating film 112 interposed between the gate electrode 113 and the semiconductor substrate 111. A source region 115 is formed on one side of the gate electrode 113 on the semiconductor substrate 111 via a source extension region 114. A drain region 117 is formed on another side of the gate electrode 113 on the semiconductor substrate 111 via a drain extension region 116. The source extension region 114 and the drain extension region 116 are both formed in a state of overlapping a lower part of the gate electrode 113.
When the gate length LG of the planar type MOSFET 101 is shortened by a scaledown, a so-called short channel effect appears. To suppress the short channel effect needs a scaledown conforming to a scaling law. That is, a scaledown needs to be performed with a combination of an increase in gate capacitance (reduction in thickness of the gate insulating film), an increase in channel concentration, and a reduction in depth of junctions of a source and a drain diffusion layer.
In achieving a scaledown while improving performance, a setting combining the three parameters described above is important. For example, according to a condition equation of J. R. Brews for occurrence of the short channel effect, channel length Lmin as a boundary determining whether the short channel effect occurs or not can be defined by one parameter γ. It is shown that the parameter is a function of three variables of increase in gate capacitance (reduction in thickness of the gate oxide film), channel concentration, and the depth of the source and drain diffusion layers. It is known that there is an infinite number of combinations of the three variables determining one value of the parameter γ, that is, increase in gate capacitance (reduction in thickness of the gate oxide film), channel concentration, and the depth of the source and drain diffusion layers.
Thus, when the junction depth can be made to be zero by devising a structure, requirements for the two other structural factors, that is, increase in gate capacitance (reduction in thickness of the gate oxide film) and increase in channel concentration can be greatly relaxed. The junction depth of a source and a drain diffusion layer significant in operation of a MOS transistor is a depth measured from an interface between a gate insulating film and a semiconductor substrate of the MOS transistor.
The above-described increase in gate capacitance has been achieved by reducing the thickness of the gate insulating film in the related art, but has reached a limit from a viewpoint of withstand voltage because physical film thickness is already less than two nm. Thus, studies have been under way to use an insulating film with a high dielectric constant, for example hafnium oxide, hafnium nitride or the like as means for increasing the capacitance without relying on further reduction of the thickness of the gate insulating film. As for increase in channel concentration, the impurity concentration of a channel region has reached 1018 cm−3. When the impurity concentration approaches 1018 cm−3, there are fears of a decrease in junction withstand voltage due to Zener breakdown (tunnel breakdown), a decrease in mobility due to a high electric field generated at a channel, and the like.
On the other hand, as for reduction in depth of the junctions of the source and drain diffusion layers, the junction depth of the shallow source and drain diffusion layers (extension) in contact with the channel has now reached 100 nm or less. When a current path is narrowed by making the junctions shallower, the series resistance of the source and drain diffusion layers is increased, and thus on current (current driving power) is decreased. However, further pursuing such reduction in depth of the junctions in the existing planar type MOS transistor has many difficult problems of doping with an impurity, lowering of temperature in subsequent heat treatment, and the like.
Accordingly, a structure having a gate 212 in a bottom part of a groove formed by etching a semiconductor substrate 211, which structure is referred to as a recess gate type (or grooved gate type), as shown in FIG. 26 has been proposed as means for achieving both the suppression of the short channel effect and the reduction of the resistance of the source and drain (see Japanese Patent Laid-Open No. Sho 49-126281 and Japanese Patent Laid-Open No. 2000-82813 as Patent Documents 1 and 2, for example).
In addition, a structure referred to as an elevated source/drain extension type (or a raised source/drain extension type) as shown in FIG. 27 has been proposed (see Patent Document 2, also see Japanese Patent Laid-Open No. 2001-144290 and Japanese Patent Laid-Open No. 2001-284468 as Patent Documents 3 and 4, for example). In this structure, a gate 312 is formed on the surface of a semiconductor substrate 311, while a source and a drain diffusion layer 313 and 314 and extension regions 315 and 316 are formed by a semiconductor layer grown by epitaxial growth on the semiconductor substrate 311.
One typification in these structures is to set the diffusion depth (Xj) of the source and drain diffusion layers to zero or a negative value. It has been confirmed by experiment that such design suppresses the short channel effect and greatly reduces the roll-off of threshold voltage. However, high on current is not obtained. This is because a corner part exists between a channel region and an overlap region.
At the corner part, local threshold voltage is raised because the effective thickness of oxide film is increased, and an electric field extends radially from the gate to the inside of the substrate, for example. Further, because electric lines of force extend radially, sheet carrier density at the corner part is lowered as compared with a flat channel region even with a same gate voltage. When the sheet carrier density is lowered, from continuity of drain current, carriers at the corner part need to run at a high speed. As a result, mobility is decreased, and the resistance of the part is increased. When the resistance is increased, a voltage drop at the corner part is increased, and thus a voltage drop at a source end and a drain end of the channel is increased.
The increase in voltage drop at the source end reduces effective gate voltage (gate-to-source voltage of an intrinsic FET). As a result, the carrier density of the channel is decreased, and the resistance is increased, so that the drain current is decreased. When the drift velocity of carriers reaches saturation, the corner part acts as a constant-current source, and thus the drain current is not increased any further. The increase in voltage drop at the drain end hinders an increase in potential at the drain end of a gate flat part, and thus drain voltage is mainly applied between the corner part on the drain side and a drain electrode. As a result, the drain side from the drain side corner part operates as a parasitic transistor. Thus, the drain current is determined by an amount of current injected into the drain side corner part, and the drain current cannot be increased effectively even when the drain voltage is increased.
On the other hand, various structures have been proposed in which a source and a drain impurity are diffused to a certain depth at gate ends while a source and a drain are raised (see Japanese Patent Laid-Open No. 2001-326351 as Patent Document 5, for example). In such an example, a corner part is buried in a source and a drain diffusion layer. Therefore, even at the corner part, sufficient sheet carrier density is secured with carriers originating from the impurity. Thus the above-described problem does not occur. However, as long as junction depth is 10 nm to 20 nm, the short channel effect when gate length is 10 nm to 20 nm cannot be sufficiently suppressed. As a result, increase in leakage current during an off time or, when the leakage current is suppressed, a decrease in on current due to a lack of overdrive voltage is inevitable. Therefore a high-performance MOSFET cannot be obtained.
Further, it has been found from calculations by the inventors that when compatibility between the suppression of the short channel effect and current driving power is to be achieved with such a structure, a permissible variation range of diffusion depth of the source and drain diffusion layers and gate length is a few nm or less, thus requiring very high controllability. Because it is not easy to obtain such high controllability, to obtain a high yield requires advanced lithography techniques and advanced impurity introduction and activation techniques, thus inviting an increase in process manufacturing cost.
In order to suppress leakage current during an off time sufficiently, threshold voltage needs to be set to a value higher than 0 V by a certain degree even when the transistor is scaled down. On the other hand, when a gate oxide film is made thinner by scaling, power supply voltage needs to be lowered to suppress a gate leak. As a result, due to the scaledown, the overdrive voltage of the gate needs to be lowered. This lowers the current driving power. Accordingly, various techniques for improving mobility to compensate for this have been devised. For example, a mobility improving technique using a change in band structure due to stress and a technique using different crystal faces where carrier mobility is highest for an NMOS and a PMOS are known.
In the technique using stress, the band structure of a channel region is changed by compressive or tensile stress occurring in the channel region at an operating temperature, and the mobility of channel carriers is increased by decreasing effective mass or scattering probability. For the stress, a large number of methods are known, including a method of coating a transistor with a thin film having a different coefficient of thermal expansion from that of a substrate or a method of forming a source and a drain region using a material having a different coefficient of thermal expansion from that of a substrate.
As for the technique using different crystal faces, a method utilizing a substrate laminating technique to use a (100) surface for an NMOS and a (110) surface for a PMOS is known.
However, when these mobility improving techniques are to be applied to a “V-shaped MOSFET” as a derivative of the grooved gate structure, for example, the following problems are expected to arise. In both cases of the method using a thin film and the method of using a source and a drain region, the channel can be distorted most efficiently when the surface of the channel is close to the surface of the substrate and is parallel to the surface of the substrate. However, the channel surface of a V-shaped channel extends in a deep portion of the substrate, and is not parallel with the principal surface of the substrate. Therefore it is not easy to generate stress in the direction of the channel efficiently. Further, for the V-shaped channel, a deep V-shaped trench needs to be formed in the surface of the substrate. Hence, a SOI substrate cannot be used, and thus freedom of a combination of surface orientations is restricted. It is thus difficult to achieve both the suppression of the short channel effect and the improvement of mobility.